1. Field of the Invention
The present invention relates generally to dielectric structures employed within microelectronic fabrications. More particularly, the present invention relates to diffusion inhibited dielectric structures employed with respect to diffusion enhanced conductor layers within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers. As microelectronic fabrication integration levels have increased and microelectronic device and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly common in the art of microelectronic fabrication to employ copper containing microelectronic conductor materials when forming patterned microelectronic conductor layers within microelectronic fabrications. Copper containing microelectronic conductor materials are desirable in the art of microelectronic fabrication when forming patterned microelectronic conductor layers within microelectronic fabrications insofar as copper containing microelectronic conductor materials are generally recognized as superior to other types of microelectronic conductor materials which may be employed within microelectronic fabrications, such as but not limited to aluminum containing microelectronic conductor materials and tungsten containing microelectronic conductor materials which may be employed within microelectronic fabrications, particularly with respect to characteristics such as but not limited to electromigration resistance characteristics and electrical current carrying characteristics.
While copper containing microelectronic conductor materials are thus desirable in the art of microelectronic fabrication for forming patterned microelectronic conductor layers within microelectronic fabrications, copper containing microelectronic conductor materials are nonetheless not entirely without problems in the art of microelectronic fabrication for forming patterned microelectronic conductor layers within microelectronic fabrications. In that regard, copper containing microelectronic conductor materials when employed when fabricating patterned copper containing microelectronic conductor layers within microelectronic fabrications are often susceptible to interdiffusion effects, in particular with respect to silicon oxide dielectric materials which are employed for passivating microelectronic devices within microelectronic fabrications, such that there is consequently realized a compromise of the dielectric properties of the dielectric materials and a related compromise of electrical properties of the microelectronic devices.
It is thus desirable in the art of microelectronic fabrication to provide methods and materials for forming within microelectronic fabrications diffusion inhibited microelectronic dielectric structures, in particular with respect to diffusion enhanced microelectronic conductor layers, such as but not limited to copper containing diffusion enhanced microelectronic conductor layers.
It is towards the foregoing object that the present invention is directed.
Various methods and materials have been disclosed in the art of microelectronic fabrication for forming microelectronic layers, and more particularly microelectronic conductor layers, and yet more particularly copper containing microelectronic conductor layers, with desirable properties within the art of microelectronic fabrication.
For example, Dubin et al., in U.S. Pat. No. 5,891,513, discloses an electroless deposition method for efficiently forming within a microelectronic fabrication a copper containing microelectronic conductor layer upon a barrier layer within the microelectronic fabrication. To realize the foregoing result, the electroless deposition method first employs a contact displacement deposition method for forming a copper activation layer upon the barrier layer prior to forming upon the copper activation layer the copper containing microelectronic conductor layer while employing the electroless deposition method.
In addition, Hong et al., in U.S. Pat. No. 6,008,117, discloses a method for forming within a microelectronic fabrication a diffusion barrier layer for inhibiting diffusion of a copper containing microelectronic conductor layer with respect to a silicon oxide dielectric layer within the microelectronic fabrication such that there is not compromised the resistive-capacitive delay characteristics of the microelectronic fabrication. In order to realize the foregoing object, the method employs forming a metal layer over the microelectronic fabrication and forming while employing an in-situ nitridation or oxidation of the metal layer a dielectric barrier layer therefrom, prior to forming the copper containing microelectronic conductor layer thereupon.
Finally, Moslehi, in U.S. Pat. No. 6,016,000, discloses a multi-level interconnected semiconductor integrated circuit microelectronic fabrication comprising a series of patterned microelectronic conductor interconnect layers interconnected with a series of patterned microelectronic conductor stud layers, wherein there is analogously also optimized resistive-capacitive delay characteristics within the multi-level interconnected semiconductor integrated circuit microelectronic fabrication. In order to realize the foregoing object, the multi-level interconnected semiconductor integrated circuit microelectronic fabrication employs a free space medium, such as but not limited to air or helium, rather than a condensed dielectric material, such as but not limited to silicon oxide, as a dielectric material interposed between the series of patterned conductor interconnect layers which is separated and interconnected by the series of patterned conductor stud layers.
Desirable in the art of microelectronic fabrication are additional methods and materials for forming within microelectronic fabrications diffusion inhibited microelectronic dielectric structures, in particular with respect to diffusion enhanced microelectronic conductor layers, such as but not limited to copper containing diffusion enhanced microelectronic conductor layers, such as to provide enhanced passivation of microelectronic devices within microelectronic fabrications.
It is towards the foregoing object that the present invention is directed.
A first object of the present invention is to provide a method for forming within a microelectronic fabrication a diffusion inhibited microelectronic dielectric structure interposed between a microelectronic conductor layer and a microelectronic device.
A second object of the present invention is to provide a method in accord with the first object of the present invention, which method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for forming a microelectronic fabrication, as well as the microelectronic fabrication which results from the method for forming the microelectronic fabrication. To practice the method of the present invention, there is first provided a substrate. There is then formed over the substrate a microelectronic device passivated with a patterned first dielectric layer in turn annularly surrounded by a patterned second dielectric layer. There is also formed over the substrate a patterned conductor layer separated from the microelectronic device by the patterned first dielectric layer and the patterned second dielectric layer. Within the method of the present invention: (1) the patterned first dielectric layer is formed from a first dielectric material having a first diffusion coefficient with respect to a conductor material from which is formed the patterned conductor layer; (2) the patterned second dielectric layer is formed from a second dielectric material having a second diffusion coefficient with respect to the conductor material from which is formed the patterned conductor layer; and (3) the first diffusion coefficient is greater than the second diffusion coefficient.
The present invention provides a method for forming within a microelectronic fabrication a diffusion inhibited microelectronic dielectric structure interposed between a microelectronic conductor layer and a microelectronic device. The method of the present invention realizes the foregoing object by forming over a substrate: (1) a microelectronic device passivated with a patterned first dielectric layer in turn annularly surrounded by a patterned second dielectric layer; and (2) a patterned conductor layer separated from the microelectronic device by the patterned first dielectric layer and the patterned second dielectric layer, wherein: (1) the patterned first dielectric layer is formed from a first dielectric material having a first diffusion coefficient with respect to a conductor material from which is formed the patterned conductor layer; (2) the patterned second dielectric layer is formed from a second dielectric material having a second diffusion coefficient with respect to the conductor material from which is formed the patterned conductor layer; and (3) the first diffusion coefficient is greater than the second diffusion coefficient.
The method of the present invention is readily commercially implemented. As will be illustrated in greater detail within the context of the Description of the Preferred Embodiment which follows, the present invention employs methods and material as are otherwise generally conventional in the art of microelectronic fabrication, but employed within the context of specific constraints and geometric configurations to provide the present invention. Since it is thus a novel order of methods and construction of materials which provides at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.